The system defaults to sleep. A low-power timer acts as an alarm clock on perpetual snooze, waking Phoenix every ten minutes for 1/10th of a second to run a set of 2,000 instructions. The list includes checking the sensor for new data, processing it, compressing it into a sort of short-hand, and storing it before going back to sleep.
The timer “isn’t an atomic clock,” Hanson said. “We keep time to 10 minutes plus or minus a few tenths of a second. For the applications this is designed for, that’s okay. You don’t need absolute accuracy in a sensor. We’ve traded that for enormous power savings.”
A unique power gate design is an important part of the sleep strategy. Power gates block the electric current from parts of a chip not essential for memory during sleep.
In typical state-of-the-art chips, power gates are wide with low resistance to let through as much electric current as possible when the device is turned on. These chips wake up quickly and run fast, but a significant amount of electric current leaks through in sleep mode.
Phoenix engineers used much narrower power gates that restrict the flow of electric current. That strategy, coupled with the deliberate use of an older process technology, cut down on energy leaks.
Of course if you read between the lines, the 1:6000 duty cycle pretty much says it all. Actually running the processor takes 180 microwatts or so, which is way less than a Core Duo but still a pile of energy. I’d like to see one that runs of some kind of scavenged mechanical power — this would be particularly useful for the kinds of sensor applications they talk about, because during interesting events there will almost certainly be more power to scavenge and you could run a faster cycle.